Bézier Curve Rendering on Virtex(tm)

The Virtex FPGA introduces new features which support the design of large systems using a synthesis flow. With much improved routing, features like clock DLLs and BlockRAM, a rich collection of resources are available to designers. We investigate how synthesis friendly Virtex is by implementing the Bézier function in a variety of ways, making use of BlockRAM, clock DLLs and shift-register LUTs. These features now make it possible to directly implement recursive algorithms in hardware, opening up previous infeasible but exotic algorithms for FPGA implementation.